This invention relates to semiconductor memory devices, and more particularly to an improved sense amplifier circuit for use in dynamic memory devices.
Dynamic MOS read/write memory devices using N-channel circuits have been constructed generally as shown in U.S. Pat. No. 3,940,747 (a 4K dynamic RAM) issued to Kuo, U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, all assigned to Texas Instruments.
In these and other prior devices a differential sense amplifier circuit was used to detect the data bit stored in a cell capacitor, and to write into or restore the data in the cells. In a typical write operation, the data on the bit lines and sense amplifier output may have to be switched from a full rail-to-rail condition one way to full rail-to-rail the other way. Usually intermediate buffers are employed which are capable of writing opposite data to the columns, and these buffers must use large transistors in order to reduce the write cycle timing.
It is the principal object of this invention to provide improved sense amplifier circuitry for high density dynamic RAM devices, particularly for high speed write operations. Another object is to provide sense amplifier circuitry for a dynamic RAM in which data can be written to the the bit lines at high speed without requiring large driver transistors in an intermediate buffer.